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Intel® MPI Library Collective Optimization on the Intel® Xeon Phi™...
AbstractThis paper discusses a methodology for optimizing Message Passing Interface (MPI) collective performance for programming applications linked with Intel® MPI Library. Intel MPI Library...
View ArticleCase Study: Optimized Code for Neural Cell Simulations
Intel held the Intel® Modern Code Developer Challenge that had students from around to world look at the code for cell clustering and 3D movement. Their task was to modify the algorithms for parallel...
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Memory Management Optimizations on the Intel® Xeon Phi™ Coprocessor Using...
Download PDFDownload Code Sample tarfileAbstractThis paper examines software performance optimization for an implementation of a non-library version of DGEMM executing in native mode on the Intel® Xeon...
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Putting Your Data and Code in Order: Data and layout - Part 2
In this pair of articles on performance and memory covers basic concepts to provide guidance to developers seeking to improve software performance. These articles specifically address memory and data...
View ArticleHow to detect Knights Landing AVX-512 support (Intel Xeon Phi processor)
The Intel Xeon Phi processor, code named Knights Landing, is part of the second generation of Intel Xeon Phi products. Knights Landing supports AVX-512 instructions, specifically AVX-512F...
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IDF'15 Webcast: Data Analytics and Machine Learning
This Technology Insight will demonstrate how to optimize data analytics and machine learning workloads for Intel® Architecture based data center platforms.Speaker: Pradeep Dubey Intel Fellow, Intel...
View ArticleEnabling IP over InfiniBand* on the Intel® Xeon Phi™ Coprocessor
IntroductionInfiniBand (IB) networking offers a high throughput and low latency. To use IB, network applications must use IB verb APIs. Traditional IP network applications cannot run on an IB network...
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MCDRAM (High Bandwidth Memory) on Knights Landing – Analysis Methods & Tools
The Intel’s next generation Xeon Phi™ processor family x200 product (code-name Knights Landing) brings in new memory technology, a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in...
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Whatever the Weather: The Intel Five Step Framework for Code Modernization
Weather forecasting is a crucial aspect of modern life, enabling efficient planning and logistics, while also protecting life and property through timely warnings of severe conditions. But accurate,...
View ArticleOption "-z defs" is no longer needed to detect missing symbols in...
Prior to Intel® Compiler 15.0 in the offload compilation model, the binaries targeting the Intel MIC Architecture were generated as dynamic libraries (.so). Dynamic libraries do not need all referenced...
View ArticleIntel® Parallel Studio XE 2017 Beta
ContentsHow to enroll in the Beta programWhat's New in the 2017 BetaFrequently Asked QuestionsBeta duration and scheduleSupportBeta webinarsBeta Release NotesKnown issuesNext stepsHow to enroll in the...
View ArticleIntel® C++ Compiler 17.0 Release Notes
This page provides links to the current Release Notes for the Intel® C++ Compiler 17.0 component of Intel® Parallel Studio XE 2017 for Windows*, Linux* and OS X*. To get product updates, log in to the...
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Developer Access Program for Intel® Xeon Phi™ Processor codenamed Knights...
Intel is bringing to market, in anticipation of general availability of the Intel® Xeon Phi™ Processor (codenamed Knights Landing), the Developer Access Program (DAP). DAP is an early access program...
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Weather Research and Forecasting Model Optimized for Knights Landing
The Weather Research and Forecasting (WRF) Model is a numerical weather prediction (NWP) system designed for both atmospheric research and operational forecasting needs. It is made up of about a half...
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Classical Molecular Dynamics Simulations with LAMMPS Optimized for Knights...
LAMMPS is an open-source software package that simulates classical molecular dynamics. As it supports many energy models and simulation options, its versatility has made it a popular choice. It was...
View ArticleOpen Source Downloads
This article makes available third-party libraries, executables and sources that were used in the creation of Intel® Software Development Products or are required for operation of those. Intel provides...
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Process and Thread Affinity for Intel® Xeon Phi™ Processors x200
The Intel® MPI Library and OpenMP* runtime libraries can create affinities between processes or threads, and hardware resources. This affinity keeps an MPI process or OpenMP thread from migrating to a...
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Recognizing and Measuring Vectorization Performance
Vectorization promises to deliver as much as 16 times faster performance by operating on more data with each instruction issued. The code modernization effort aims to get all software running faster by...
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Migrating Applications from Knights Corner to Knights Landing Self-Boot...
While there are many different programming models for the Intel® Xeon Phi™ coprocessor (code-named Knights Corner (KNC)), this paper lists the more prevalent KNC programming models and further...
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Performance Improvement Opportunities with NUMA Hardware
Intel Corporation’s non-uniform memory access (NUMA) strategy is based on several new memory technologies that promise significant improvements in both capability and performance:Multi-Channel DRAM...
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