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Modern Memory Subsystems Benefits for Data Base Codes, Linear Algebra Codes,...
The overall advantages of Multi-Channel DRAM (MCDRAM) and High-Bandwidth Memory (HBM) are:They offer higher bandwidth to Intel® Xeon Phi™ cores than is available from off-package dynamic random-access...
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How to use offload over fabric with Knights Landing (Intel® Xeon Phi™ processor)
Offload over Fabric overviewThe Intel® Xeon Phi™ coprocessors x100, code named Knights Corner, support the offload programming model, allowing users to offload computations over PCIe and build...
View ArticleIntel® Xeon Phi™ Processor Applications Performance Proof Points
This presentation is an expanding collection of Intel® Xeon Phi™ processor test cases or “proof points” that demonstrate improved software performance for key applications and benchmarks in key...
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Recipe: LAMMPS* for Intel® Xeon Phi™ Processors
PurposeThis code recipe describes how to get, build, and use the LAMMPS* code with best performance on Intel® Xeon® and Intel® Xeon Phi™ processors along and with some performance...
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Recipe: Using Binomial Option Pricing Code as Representative Pricing...
IntroductionThe Binomial Options Pricing Model (BOPM) is a generalized numerical method used to value options in the quantitative financial services industry. Specifically, it is a lattice-based...
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Recipe: Monte Carlo European Option Pricing for Intel® Xeon Phi® Processor
IntroductionThis is the second of a two document series. The first article, Monte Carlo European Option Pricing with RNG Interface for Intel® Xeon Phi™ Processor, covers the background of Monte Carlo...
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Recipe: Building and Running MASNUM WAVE for Intel® Xeon Phi™ Processors
I. OverviewThis article provides a recipe for how to obtain, compile, and run an optimized version of MASNUM WAVE (0.2 degree high resolution) workload on Intel® Xeon® processors and Intel® Xeon Phi™...
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Recipe: Pricing Options Using Barone-Adesi Whaley Approximation
IntroductionMany people have discussed how parallel programming practice can be applied to the Black-Scholes model and the Black-Scholes formula that prices European options analytically. They have...
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Recipe: The Black-Scholes-Merton Formula Optimization for Intel® Xeon Phi™...
IntroductionFinancial derivative pricing is a cornerstone of quantitative finance. The most common form of financial derivatives is common stock options, which are contracts between two parties...
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Tutorial on Intel® Xeon Phi™ Processor Optimization
Download File[TAR 20KB]1. IntroductionIn this tutorial, we demonstrate some possible ways to optimize an application to run on the Intel® Xeon Phi™ processor. The optimization process in this tutorial...
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Boost Performance and Energy Efficiency on HPC Workloads with Intel® Xeon...
Testing on LAMMPS demonstrates the potential for demanding applications.Modernizing code with increased parallelism not only allows software to take advantage of the full breadth of Intel® architecture...
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Recipe: Building and Running VLPL-S for Intel® Xeon Phi™ Processors
I. OverviewThis article provides a recipe for how to obtain, compile, and run an optimized version of VLPL-S on Intel® Xeon® processors and Intel® Xeon Phi™ processors.The source for this version of...
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Recipe: RELION for Intel® Xeon Phi™ 7250 processor
I. OverviewThis article provides a recipe for how to obtain, compile, and run an optimized version of relion-1.4 on Intel® Xeon® processors and Intel® Xeon Phi™ processors.The source for this version...
View ArticleOptimizing Memory Bandwidth in Knights Landing on Stream Triad
OverviewThis document demonstrates the best methods to obtain peak memory bandwidth performance on Intel® Xeon Phi™ Processor (codenamed Knights Landing). This is done using STREAM* benchmarks, the de...
View ArticleIntel Inside. Software Optimization Outside on the Intel® Xeon Phi™ Product...
Experts from Allinea, Altair, Convergent Science, and Kitware share some of the use cases and explore the significant advantages of running their applications on the Intel® Xeon Phi™ product...
View ArticleCompiling for the Intel® Xeon Phi™ processor and the Intel® AVX-512 ISA
IntroductionThis document briefly gives an overview of the Intel® Advanced Vector Extensions 512 (Intel® AVX-512) and shows different ways to build an application for the Intel® Xeon Phi™ processor...
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Recipe: ROME1.0/SML for the Intel® Xeon Phi™ Processor 7250
OverviewThis article provides a recipe for how to obtain, compile, and run ROME1.0 SML on Intel® Xeon® processors and Intel® Xeon Phi™ processors. Before you run SML, you need to run the MAP processing...
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Recipe: Building and Running YASK (Yet Another Stencil Kernel) on Intel®...
OverviewYASK, Yet Another Stencil Kernel, is a framework to facilitate design exploration and tuning of HPC kernels including vector folding, cache blocking, memory layout, loop construction, temporal...
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Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques
Improving the computational performance of a deep learning frameworkPDF versionAuthorsVadim Karpusenko, Ph.D., Intel Corporation Andres Rodriguez, Ph.D., Intel Corporation Jacek Czaja, Intel...
View ArticleCase Study: Many-Fermion Dynamics using Intel® Xeon Phi™ Processors
Many-Fermion Dynamics---nuclear, or MFDn, is a configuration interaction (CI) code for nuclear structure calculations. It is a platform independent Fortran 90 code using a hybrid MPI/ OpenMP*...
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