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Books - High Performance Parallelism Pearls
The two “Pearls” books contain an outstanding collection of examples of code modernization, complete with discussions by software developers of how code was modified with commentary on what worked as...
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ANSYS* Scales Simulation Performance
The Need for Speed in Simulation-Based DesignEngineering simulation software has changed how companies design products, enabling them to explore and test more design options faster, while reducing the...
View ArticleAttend IDF'15: HPC Developer Showcase
Intel has just launched the Intel® Modern Code Developer Community to help HPC developers code for maximum performance on current and future hardware. The initiative is targeted to more than 400,000...
View ArticleProgramming and Compiling for Intel® Many Integrated Core Architecture
Compiler Methodology for Intel® MIC ArchitectureThis article is part of the Intel® Modern Code Developer Community documentation which supports developers in leveraging application performance in code...
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A Structured Performance Optimization Framework for Simultaneous...
Heterogeneous computing platforms with multicore host system and many-core accelerator devices have taken a major step forward in the mainstream HPC computing market this year with the announcement of...
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Optimizing Legacy Molecular Dynamics Software with Directive-based Offload
Directive-based programming models are one solution for exploiting many-core coprocessors to increase simulation rates in molecular dynamics. They offer the potential to reduce code complexity with...
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Better Concurrency and SIMD On The HIROMB‐BOOS‐Model 3D Ocean Code
By utilizing the strengths of the Intel® Xeon Phi™ coprocessor, the chapter 3 High Performance Parallelism Pearls authors were able to improve and modernize their code and “achieve great scaling,...
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Optimization Techniques for the Intel® MIC Architecture: Part 3 of 3
AbstractThis is part 3 of a 3-part educational series of publications introducing select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon®...
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Optimization Techniques for the Intel® MIC Architecture: Part 1 of 3
AbstractThis is part 1 of a 3-part educational series of publications introducing select topics on optimization of applications for the Intel multi-core and manycore architectures (Intel® Xeon®...
View ArticleIntel(R) Manycore Platform Software Stack (MPSS) - Long-Term-Support Archive
In this page you will find the last releases of the Intel(R) Manycore Platform Software Stack (MPSS) Long Term Support product (LTS). The most recent release is found here:...
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Debugging Intel® Xeon Phi™ Applications on Windows* Host
ContentsIntroductionDebug Solution for Intel® MICHow to get it?Debug Solution as IntegrationComponents RequiredConfigure & TestPrerequisite for DebuggingDebugging Applications with Offload...
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Debugging Intel® Xeon Phi™ Applications on Linux* Host
ContentsIntroductionDebug Solution for Intel® MICHow to get it?Why use GNU* GDB provided by Intel?Why is Intel providing a Command Line and Eclipse* IDE Integration?FeaturesRegister and Instruction Set...
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A Brief Survey of NUMA (Non-Uniform Memory Architecture) Literature
This document presents a list of articles on NUMA (Non-uniform Memory Architecture) that the author considers particularly useful. The document is divided into categories corresponding to the type of...
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Finite Differences on Heterogeneous Distributed Systems
Download Zip Source CodeHere we exemplify how to expand Finite Difference (FD) computational kernels to run on distributed systems. Additionally, we describe a technique that shows how to deal with the...
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Slash Your MSC Nastran* Simulation Runtimes by Up to 50 Percent
Doubling performance for your most complex MSC Nastran* simulations can deliver a range of high-value options for your engineering and design teams. You may be able to obtain results hours or even days...
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IDF'15 Webcast: Data Analytics and Machine Learning
This Technology Insight will demonstrate how to optimize data analytics and machine learning workloads for Intel® Architecture based data center platforms.Speaker: Pradeep Dubey Intel Fellow, Intel...
View ArticleIntel® Xeon® Phi™ X200 Family Processor Performance Monitoring Reference Manual
The Intel® Xeon® Phi™ X200 Family processor (code name Knights Landing) provides performance monitoring facilities that are a unique combination of Intel® Atom™ processor-like core performance...
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Intel® Xeon Phi™ Coprocessor Performance Proof Points
This presentation is an expanding collection of Intel® Xeon Phi™ coprocessor test cases or “proof points” that demonstrate improved software performance for key applications and benchmarks in key...
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Get a Helping Hand from the Vectorization Advisor
Get a Helping Hand from the Vectorization AdvisorIf you have not tried the new Vectorization Advisor yet, you might find this story of how it helped one customer sufficiently motivating to give it a...
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High-Performance, Modern Code Optimizations for Computational Fluid Dynamics
Modern server farms consist of a large number of heterogeneous, energy-efficient, and very high-performance computing nodes connected with each other through a high-bandwidth network interconnect....
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