Assigning physical hard drives to Intel® Xeon Phi™ coprocessors
Intel® Xeon Phi™ coprocessors are able to directly mount and use block devices that are attached to the host system. This article provides basic instructions for formatting and mounting a hard disk...
View ArticleCheck Intel® Xeon Phi™ Coprocessors with Intel® Cluster Checker 2.2
Intel® Cluster Checker tool evaluates HPC clusters for consistency, functionality and performance. This includes capability for evaluating the hardware configuration of Intel® Xeon Phi™...
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What public disclosures has Intel made about Knights Landing?
Knights Landing is the codename for Intel's 2nd generation Intel® Xeon Phi™ Product Family, which will deliver massive thread parallelism, data parallelism and memory bandwidth – with improved...
View ArticlepyMIC: A Python Offload Module for the Intel(R) Xeon Phi(TM) Coprocessor
Python has gained a lot of attention by the high performance computing community as an easy-to-use, elegant scripting language for rapid prototyping and development of flexible software. At the same...
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Debugging Intel® Xeon Phi™ Applications on Linux* Host
ContentsIntroductionDebug Solution for Intel® MICHow to get it?Why use GNU* GDB provided by Intel?Why is Intel providing a Command Line and Eclipse* IDE Integration?Deprecation NoticeFeaturesRegister...
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Debugging Intel® Xeon Phi™ Applications on Windows* Host
ContentsIntroductionDebug Solution for Intel® MICHow to get it?Debug Solution as IntegrationComponents RequiredConfigure & TestPrerequisite for DebuggingDebugging Applications with Offload...
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Power Management Policy
By Taylor Kidd, Intel CorporationThis article is essentially a collection of blogs I wrote on the same subject. The differences are simply a degree of formalism.TABLE OF CONTENT:Preface: Power...
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Optimizing Execution Performance for an Isotropic Double Precision 3DE Finite...
AbstractThis paper discusses applying programming restructuring transformations to a baseline 3D stencil application so that the stencil executable can exploit the architectural features of the Intel®...
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LAMMPS* for Intel® Xeon Phi™ Coprocessor
PurposeThis code recipe describes how to get, build, and use the LAMMPS* code for the Intel® Xeon Phi™ coprocessor.IntroductionLarge-scale Atomic/Molecular Massively Parallel Simulator (LAMMPS*) is a...
View ArticleBLAST for the Intel® Xeon Phi™ Coprocessor
PurposeThis code recipe describes how to get, build, and use the BLAST+ code that includes support for the Intel® Xeon Phi™ coprocessor with Intel® Many-Integrated Core (MIC)...
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miniGhost on Intel® Xeon® processors and Intel® Xeon Phi™ Coprocessor
PurposeThis article provides instructions for code access, build, and run directions for the miniGhost code, running on Intel® Xeon® processors and Intel® Xeon Phi™ Coprocessors.IntroductionminiGhost...
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Combine ANSYS Mechanical with the Intel® Xeon Phi™ coprocessor for dramatic...
Download PDF[PDF 224KB]Incremental performance gains for engineering simulations can improve productivity and shrink product development timelines and time to market. Doubling performance can transform...
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High Bandwidth Memory (HBM): how will it benefit your application?
PurposeThe first step towards the usability of MCDRAM or High Bandwidth Memory (HBM) is assessing the memory bandwidth utilization for your application.This article provides basic instructions on how...
View ArticleAn Embree-Based Viewport Plugin for Autodesk Maya* 2014 with Support for the...
Download PDFPurposeThis code recipe describes how to obtain, build, and use the Embree-based Viewport Plugin for Autodesk Maya* 2014 on either Microsoft Windows* or Linux*. This plugin (actually a...
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Special Promotion for ANSYS Developers: Intel® Xeon Phi™ Coprocessors
Special Promotion for ANSYS Developers: Intel® Xeon Phi™ Coprocessors ANSYS* and Intel worked closely together to deliver up to 2.2x higher performance, for ANSYS Mechanical* R16.0, by optimizing the...
View ArticleBitonic Sorting
Sample for Windows*Sample for Linux*Download DocumentationFeatures / DescriptionDemonstrates how to implement an efficient sorting routine with the OpenCL™ technology.Operates on arbitrary input array...
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Using SPIR for fun and profit with Intel® OpenCL™ Code Builder
IntroductionWhat is SPIR?How is SPIR binary different from Intermediate Binary?How to produce SPIR binary with an Intel command line compiler?How to produce SPIR binary with Intel® INDE's Kernel...
View ArticleIntel® Code Modernization Enablement Program
Intel® Code Modernization Enablement Program for DevelopersIntel is introducing the Intel® Code Modernization Enablement Program for Developers. Code modernization allows software traditionally...
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Calculating “FLOP” using Intel® Software Development Emulator (Intel® SDE)
PurposeFloating point operations (FLOP) rate is used widely by the High Performance Computing (HPC) community as a metric for analysis and/or benchmarking purposes. Many HPC nominations (e.g., Gordon...
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Debugging Intel® Xeon Phi™ Applications on Windows* Host
ContentsIntroductionDebug Solution for Intel® MICHow to get it?Debug Solution as IntegrationComponents RequiredConfigure & TestPrerequisite for DebuggingDebugging Applications with Offload...
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