Intel® Xeon Phi™ Coprocessor September 2013 Developer Webinar Q&A Responses
The third session of our High Performance Application Development for Intel® Xeon® and Intel® Xeon Phi™ processors class was held during the last week of September, and generated yet another list of...
View ArticleSymmetric Mode MPI Performance without InfiniBand*
SymptomSlow host-coprocessor MPI communications in systems with no InfiniBand* HCA. If running with I_MPI_DEBUG=2 or higher, you will see one of the following messages indicating that the TCP fabric...
View ArticleCache Blocking Techniques
Compiler Methodology for Intel® MIC ArchitectureCache Blocking TechniquesOverviewAn important class of algorithmic changes involves blocking data structures to fit in cache. By organizing data memory...
View ArticleEfficient Parallelization
Efficient Parallelization Document Compiler Methodology for Intel® MIC Architecture Efficient Parallelization OverviewThis chapter covers topics in parallelization. There are links to various...
View ArticleOpenMP Thread Affinity Control
Intel® Composer XE for MIC Compi Compiler Methodology for Intel® MIC Architecture Compiler Methodology for Intel® MIC Architecture Efficient Parallelization, OpenMP Thread Affinity ControlOverviewThe...
View ArticleOverview of Vectorization Reports and new vec-report6
Overview of vectorization report Compiler Methodology for Intel® MIC ArchitectureVectorization Essentials, Vectorization and Optimization Reports, Overview of vectorization reports and new...
View ArticleMemory Allocation and First-Touch
Compiler Methodology for Intel® MIC ArchitectureMemory Allocation and First-TouchMemory allocation is expensive on the coprocessor compared to Xeon - so it is prudent to reuse already-allocated memory...
View ArticleGetting Started with Intel® Composer XE 2013, New User Compiler Basics
Compiler Methodology for Intel® MIC Architecture Getting Started with Intel® Composer XE 2013, New User Compiler BasicsOverviewModern compilers can be invoked with hundreds of options. From these, what...
View ArticleElement wise alignment requirements for data accesses to be ABI-compliant on...
Compiler Methodology for Intel® MIC ArchitectureUnlike the IA-32 and Intel® 64 architectures, the Intel® MIC Architecture requires all data accesses to be properly aligned according to their size,...
View ArticleOpenMP Related Tips
Compiler Methodology for Intel® MIC ArchitectureOpenMP Related TipsOpenMP* Loop Collapse DirectiveUse the OpenMP collapse-clause to increase the total number of iterations that will be partitioned...
View ArticleSelective Use of gatherhint/scatterhint Instructions
Compiler Methodology for Intel® MIC ArchitectureSelective Use of gatherhint/scatterhint InstructionsOverviewThe -mGLOB_default_function_attrs=”use_gather_scatter_hint=on” compiler option can be used to...
View ArticleAdvanced Optimizations for Intel® MIC Architecture, Low Precision Optimizations
Compiler Methodology for Intel® MIC Architecture Advanced Optimizations for Intel® MIC Architecture, Low Precision OptimizationsOverviewThe latest Intel Compilers (released after the 13.0.039 Beta...
View ArticleAdvanced Optimizations for Intel® MIC Architecture
Compiler Methodology for Intel® MIC ArchitectureAdvanced OptimizationsOverviewThis chapter details some of the advanced compiler optimizations for performance on Intel® MIC Architecture AND most of...
View ArticleGetting Started with Intel® Composer XE 2013, Compiler Pragmas and Directives
Compiler Methodology for Intel® MIC Architecture Getting Started with Intel® Composer XE 2013, Compiler Pragmas and DirectivesOverviewCompiler options allow a user to control how source files are...
View ArticleVectorization Essentials
Compiler Methodology for Intel® MIC Architecture Vectorization Essentials OverviewThis chapter covers topics in vectorization. Vectorization is a form of data-parallel programming. In this, the...
View ArticleCompiling Open Source for Intel® Xeon Phi™ Coprocessors
One of the strengths of the Intel® Xeon Phi™ coprocessor is the ability to build existing software to run on the Intel® Many Integrated Core (Intel® MIC) architecture with a minimum of change (in most...
View ArticleQuick Start Guide: For the Intel® Xeon Phi™ Coprocessor Developer
This article makes recommendations for how a developer can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This is one of three articles: For the Administrator,...
View ArticleQuick Start Guide: For the Intel® Xeon Phi™ Coprocessor Administrator
This article makes recommendations for how an administrator can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This article is 1 of 3: For the Administrator, for...
View ArticleUnderstanding Gather-Scatter instructions and the -gather-scatter-unroll...
Gather-Scatter instructions may not be the optimal choice of instructions when you are trying to achieve superior performance on the Intel® Xeon Phi™ coprocessor. However, if your code uses indirect...
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Program Optimization through Loop Vectorization
Download ArticleDownload Program Optimization through Loop Vectorization [PDF 617KB]OverviewIn this white paper, we will use a very simplified finite difference stencil computation of the following...
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